The present invention relates generally to field effect transistors (FETs), and more particularly to an FET with non-uniform gate/dielectric characteristics.
The field effect transistor (FET) is well known as a fundamental component of a large variety of integrated circuits. As with integrated circuits in general, two primary goals with respect to the ongoing development of FETs are reduced size and increased speed of operation. The reduction or scaling in size has necessarily led to shorter channel lengths.
It has been found that with process technology improved to the point where devices can be fabricated with channel lengths smaller than 2 xcexcm, FET devices began to exhibit phenomena not predicted by long-channel models. Such phenomena have since been termed xe2x80x9cshort-channelxe2x80x9d effects. These short-channel effects are oftentimes undesirable and have become a major limiting factor in the scaling of FETs. For example, short-channel effects include increased dependence of the saturation drain current vs. the channel length variation; increased leakage current when the FET is in the xe2x80x9coffxe2x80x9d condition; and reliability problems. (See, e.g., S. Wolf, Silicon Processing for the VLSI Era, Vol. 3, Chap. 5, Lattice Press (1995), for discussion on short-channel effects).
The conventional approach to suppressing short-channel effects involves device engineering in the semiconductor substrate (e.g., silicon) underneath the gate dielectrics. For example, various techniques such as lightly doped drain (LDD), shallow junction, pocket ion implantation, etc. have been utilized.
Nevertheless, there is a strong need in the art for further improvements in suppressing short-channel effects in FETs. There is a strong need for a technique which goes beyond device engineering underneath the gate dielectric. In particular, there is a strong need in the art for an FET structure and method of making the same which enables even further reduction in size substantially without detriment due to short-channel effects.
The present invention relates to an FET structure, and method for making the same, which further suppresses short-channel effects based on designed variations within the gate dielectric itself. The FET structure utilizes a non-uniform gate dielectric to alter the vertical electric field presented along the channel. For example, the thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitance.
Generally speaking, the present invention proposes a new FET structure (e.g., a metal-oxide-semiconductor FET (MOSFET)). By strategically placing the same or different gate materials above various gate dielectric materials along the channel, significant improvements in many aspects of device performance can be obtained. Since existing and emerging technologies, such as electron beam (e-beam), selective/angle ion implantation, precise lithographic alignment, etc. can be used to generate well defined asymmetric gate structures and varied gate dielectrics, such technologies are particularly suited for the making a FET in accordance with the present invention.
An FET in accordance with the present invention is typified by a structure in which the gate dielectric thickness and/or dielectric constant varies along the length of the channel. The gate dielectric may have multiple thickness and/or dielectric constant changes along the channel to optimize the device performance, reliability, manufacturability, etc.
The attributes of the new structure have been analyzed. The results indicate that the structure improves short-channel effects by stabilizing threshold voltages to a fairly constant value upon scaling. In addition, the new structure suppresses drain induced barrier lowering (DIBL) to make the structure ideal for use as a current source or an active load for analog applications. Furthermore, the structure reduces punchthrough tendencies to facilitate a reduced need in substrate doping limitations. The new structure also decreases maximum electric field along the channel to overcome reliability problems, and increases the Idsat/Idsoff ratio to provide improved performance.
According to a particular aspect of the invention, a transistor is provided which includes a semiconductor substrate; a source region and a drain region formed within the semiconductor substrate; a channel region defined within the semiconductor substrate extending between the source region and the drain region; a gate dielectric layer formed on the substrate above the channel region, the gate dielectric layer having at least one of a non-uniform thickness and a non-uniform dielectric constant along a length of the channel region; and a gate material layer formed above the gate dielectric layer.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.